发明名称 Decomposer for parallel turbo decoding, process and integrated circuit
摘要 A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second mxn matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth mxn matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.
申请公布号 US2006236194(A1) 申请公布日期 2006.10.19
申请号 US20060455903 申请日期 2006.06.19
申请人 LSI LOGIC CORPORATION 发明人 ANDREEV ALEXANDER E.;SCEPANOVIC RANKO;VUKOVIC VOJISLAV
分类号 H03M13/00;H03M13/29 主分类号 H03M13/00
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