| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a synchronizing circuit attaining an improvement in timing margin. <P>SOLUTION: A first conductive type third MOS is provided between a common source for first conductive type first and second MOSs and first potential, second conductive type fourth and fifth MOSs are provided between second potential and drains of the first and second MOSs, and second conductive type sixth and seventh MOSs are provided while cross-connecting their gates and drains in parallel with the fourth and fifth MOSs. An input signal is supplied to a gate of the first MOS, a gate of the second MOS is connected to the drain of the first MOS, a clock is supplied to a gate of the third MOS , a clock of the same phase as the clocks are supplied to gates of the fourth and fifth MOSs, and first and second signals are outputted from the drains of the first and second MOSs and transported to an RS flip-flop circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT |
