发明名称 Semiconductor integrated circuit device manufacturing method
摘要 To reduce variation in channel lengths of MOS transistors within a circuit functional module. When exposure of a wafer substrate having a semiconductor integrated circuit device 1 including a plurality of CMOS circuit module regions CCM 11 to CCM 22 to be subject to substrate bias control formed in a core region 10 is performed using a step-and-scan type projection exposure apparatus, scanning is performed in the same direction as a longitudinal direction of the respective CMOS circuit module regions CCM 11 to CCM 22 . In this device, a gate insulating film is formed on the substrate, a gate electrode material film is formed on the gate insulating film, and a photoresist film is formed on the gate electrode material film.
申请公布号 US2006232300(A1) 申请公布日期 2006.10.19
申请号 US20060402862 申请日期 2006.04.13
申请人 NEC ELECTRONICS CORPORATION 发明人 OYAMADA MAKOTO
分类号 H03K19/20;H03K19/094 主分类号 H03K19/20
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