发明名称 |
METHOD FOR GENERATING A SET OF MASKS FOR MANUFACTURE OF AN INTEGRATED CIRCUIT |
摘要 |
A method and apparatus for deep sub-micron layout optimization is described. Components of an integrated circuit (IC) design (e.g., gates) can be identified and manufactured using a phase shifting process to improve circuit density and/or performance as compared to a circuit manufactured without using phase shifting processes. In one embodiment, a first mask (e.g., a phase shift mask) is generated that includes the component to be manufactured using the phase shifting process. A second mask (e.g., a trim mask) is also generated to further process the structure created using the first mask. Both masks are defined based on a region (e.g., a diffusion region) in a different layer of the integrated circuit layout than the structure (e.g., the gate) being created with the phase shifting process. |
申请公布号 |
EP1218798(B1) |
申请公布日期 |
2006.10.18 |
申请号 |
EP20000950849 |
申请日期 |
2000.07.28 |
申请人 |
MENTOR GRAPHICS CORPORATION |
发明人 |
COBB, NICOLAS, BAILEY;SAKAJIRI, KYOHEI |
分类号 |
G03F1/00;G03F1/26;G03F7/20;H01L21/027 |
主分类号 |
G03F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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