A memory controller with an adaptive timing system for controlling access to the memory

摘要

The present application provides a memory controller (212) for controlling a transfer of a datum from a data source (104) to a data destination (106). The controller comprises a delay circuit (410) configured to generate a plurality of delay clock signals at different times; a plurality of latches (412A, 412B, 412C) responsive to the plurality of delay clock signals, wherein each latch receives a timing signal from the data source and generates a latched signal corresponding to the timing signal received from the data source in response to the delay clock signal; and a compare circuit (414A, 414B) responsive to a plurality of the latched signals from the plurality of latches, wherein the compare circuit is configured to generate a comparison signal corresponding to a difference between the plurality of the latched signals.