发明名称 |
An analog equaliser characterised by iterative means arranged in operation to generate an estimate of marginal posterior expectations for received bit values |
摘要 |
<p>Prior art analog solutions to MIMO detection have the drawback that the number of transistors used increases exponentially in proportion to the number of receiver channels. The current invention aims to find a lower complexity solution to analog equalisation for applications such as MIMO detection and mass storage readers. The analog equaliser includes at least one analogue processing block (APB) arranged in operation to iteratively generate an estimate of marginal posterior expectations for received bit values. A further independent claim states that the equalisation method comprises the step of passing a plurality of log-likelihood marginal posterior expectations to an APB and generating in the APB a revised estimate of the log-likelihood marginal posterior expectations using coordinate descent optimisation.</p> |
申请公布号 |
GB2425236(A) |
申请公布日期 |
2006.10.18 |
申请号 |
GB20050007375 |
申请日期 |
2005.04.12 |
申请人 |
TOSHIBA RESEARCH EUROPE LIMITED |
发明人 |
ROBERT JAN PIECHOCKI;JOSEP VICENT SOLER GARRIDO |
分类号 |
H04H20/88;H04L25/03;H04B3/06;H04J99/00 |
主分类号 |
H04H20/88 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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