发明名称 Low latency multi-level communication interface
摘要 A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM sigsnals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a "symbol" at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
申请公布号 US7124221(B1) 申请公布日期 2006.10.17
申请号 US20000478916 申请日期 2000.01.06
申请人 发明人
分类号 G06F13/42;G11C7/10;G11C7/22;G11C11/56;H03K7/02;H04L7/033;H04L25/02;H04L25/08;H04L25/49;H04N7/24 主分类号 G06F13/42
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