发明名称 PATTERN LAYOUT OF INTEGRATED CIRCUIT, PHOTOMASK, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND DATA PRODUCING METHOD
摘要 A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.
申请公布号 KR20060108233(A) 申请公布日期 2006.10.17
申请号 KR20060032817 申请日期 2006.04.11
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MASHITA HIROMITSU;FUJISAWA TADAHITO;INOMOTO MINORU;HASHIMOTO KOJI;KAI YASUNOBU
分类号 H01L21/027;G03F1/36;G03F1/68;G03F1/70;H01L21/00;H01L21/28;H01L21/3205;H01L21/768;H01L21/82;H01L23/522 主分类号 H01L21/027
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