Method of improving lock acquisition times in systems with a narrow frequency range

摘要

The present invention adds an additional feedback loop to a phase locked loop (PLL). The additional feedback loop detects if the actual output frequency of the PLL is above or below the desired output frequency. If the actual output frequency is above the desired output frequency a signal is added to the forward path of the PLL to decrease the frequency of the PLL oscillator. If the actual output frequency is below the desired output frequency a signal is added to the forward path of the PLL to increase the frequency of the PLL oscillator.