发明名称 Execution control apparatus of data driven information processor for instruction inputs
摘要 An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that stores N (N>=2) waiting data and respective data valid flags in one address; a constant storage that stores constants and a constant valid flag; a constant readout unit that reads out a constant and a constant valid flag from the constant storage with the node number of an input packet as the address; a unit that calculates a hash address and selects a process for data waiting depending upon a combination of a data valid flag, a constant valid flag, and the number of instuction inputs; and a unit that performs a waiting process in response to a select signal.
申请公布号 US7124280(B2) 申请公布日期 2006.10.17
申请号 US20010833653 申请日期 2001.04.13
申请人 SHARP KABUSHIKI KAISHA 发明人 KAMITANI SHINGO;HATAKEYAMA KOUICHI
分类号 G06F15/82;G06F9/30;G06F9/44 主分类号 G06F15/82
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