发明名称 Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices
摘要 Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.
申请公布号 US7124161(B2) 申请公布日期 2006.10.17
申请号 US20050264778 申请日期 2005.10.31
申请人 ALTERA CORPORATION 发明人 CHOO CHANG;HAZANCHUK ASHER
分类号 G06F7/38;G06F7/52 主分类号 G06F7/38
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