发明名称 |
Isolation-region configuration for integrated-circuit transistor |
摘要 |
A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.
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申请公布号 |
US7122876(B2) |
申请公布日期 |
2006.10.17 |
申请号 |
US20040916133 |
申请日期 |
2004.08.11 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
WU YOU-KUO;CHIANG EDWARD;HSU SHUN-LIANG |
分类号 |
H01L29/00 |
主分类号 |
H01L29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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