Core logic chip conducting multi-channel data transmission

摘要

An additional data transmission channel is provided between the north bridge chip and the system memory when the graphic accelerator is integrated into the north bridge chip. The additional data transmission channel can be similar to the existent data transmission channel between the north bridge chip and the system memory for providing extensive data transmission bandwidth. Alternatively, the additional data transmission channel can be specific to the communication between the graphic accelerator in the north bridge chip and the frame buffer in the system memory.