发明名称 OUTPUT BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an output buffer circuit in which power consumption is small even when de-emphasis continues. SOLUTION: The output buffer circuit which has a pre-emphasis function, and outputs a logical signal to a transmission line which serves as a distributed constant circuit, is provided with a main buffer 8 which receives a first signal in which a logical value is given to a logical signal, and drives the transmission line, a pre-buffer 9 which receives a second signal which has a predetermined logical relation with the first signal, cooperates with the first buffer, and drives the transmission line, and a means which detects change of the logical value of the logical signal. Output impedance of the second buffer is set higher than output impedance of the first buffer in a limit to improve the attenuation value of the signal in the transmission line, in a case that the de-emphasis condition continues, a control signal is created in a data creation part 1 so as to make the second buffer cooperate with the first buffer, and drive the transmission line. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006279268(A) 申请公布日期 2006.10.12
申请号 JP20050092219 申请日期 2005.03.28
申请人 NEC CORP 发明人 NEDACHI TAKAAKI
分类号 H04L25/02;H03K19/0175;H04L25/03 主分类号 H04L25/02
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