| 摘要 |
A processing circuit for simplifying a plurality of types of synchronization signals into a single type of signal is described. The processing circuit has a first polarity converter, a second polarity converter, an extraction circuit, a removal circuit, a detection circuit, and a selection circuit. The extraction circuit extracts a vertical synchronization composition from an inputted synchronization signal on a first line. When an inputted vertical synchronization signal exists on a second line, the selection circuit outputs the inputted vertical synchronization signal, and when the inputted vertical synchronization signal doesn't exist on the second line, the selection circuit outputs the vertical synchronization composition extracted from the inputted synchronization signal.
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