| 摘要 |
<P>PROBLEM TO BE SOLVED: To control a jitter influence included in a clock generated by a PLL circuit to the minimum in a digital system which regards the clock generated by the PLL circuit as a reference clock, applies a digital process by converting an analog signal of an input signal into a digital signal, and outputs the processed result by converting it into the analog one. <P>SOLUTION: A delay time of a delay apparatus 4 is adjusted so as that a total delay time of a digital processing circuit 3 and the delay apparatus 4 is equal to a period of the jitter of the clock. As the digital-processed signal is converted into the analog signal only by the time of a multiple of the jitter period included in the reference clock after delaying it thereby, the delay time from an A/D converter 2 of an input step to a D/A converter 5 of an output step coincides with the jitter period, and the influence of the jitter included in the clock to the output analog signal is controlled to the minimum. <P>COPYRIGHT: (C)2007,JPO&INPIT |
