| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock recovery circuit of a reception circuit for receiving multivalue data that suppresses occurrence of jitter. <P>SOLUTION: Each of comparators S1, S2, S3 compares a corresponding reference voltage with an input signal, and flip-flop circuits FF1a to FF3a, FF1b to FF3b store their comparison results. A phase adjustment circuit T1 recovers three consecutive data from data stored in the flip-flop circuits FF1a to FF3a, FF1b to FF3b. When signal waveforms of the three consecutive data change to a symmetry form, a PLL circuit P1 controls a phase of a recovered clock in a change timing of the middle data in the three data, and when the signal waveform is not symmetric, the PLL circuit P1 controls no phase of the recovered clock in the change timing of the middle data but awaits a succeeding timing. <P>COPYRIGHT: (C)2007,JPO&INPIT |
