CLOCK JITTER CALCULATION DEVICE, CLOCK JITTER CALCULATION METHOD AND CLOCK JITTER CALCULATION PROGRAM

摘要

PROBLEM TO BE SOLVED: To easily determine the magnitude of jitter of a clock signal caused by power supply noise and the like. SOLUTION: A voltage drop analysis step S101 calculates temporal change in supply voltage supplied to each cell on a clock signal transmission path. A delay regulation calculation step S102 calculates variations in delay time in each cell depending on the supply voltage fluctuations. A clock delay variation calculation step S103 determines the magnitude of clock signal jitter according to the delay time variations. COPYRIGHT: (C)2007,JPO&INPIT