| 摘要 |
An address latch signal generation circuit and an address decoding circuit may generate an address latch signal capable of latching pre-decoded internal address signals. The circuits may include a plurality of address transition detectors, each of the address transition detectors receiving a plurality of internal address signals pre-decoded by a pre-decoder, detecting level transition states of the internal address signals, and generating a control signal which has a predetermined enable period; a first logic unit for performing a logic operation on the control signals received from the plurality of address transition detectors, and generating the result signal; and a latch signal output unit for performing synchronization with a disable time point of the result signal from the first logic unit, thereby generating the address latch signal.
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