发明名称 CROSSTALK CHECK METHOD
摘要 PROBLEM TO BE SOLVED: To reduce processing manhours due to crosstalk occurrence, to suppress area increase and power consumption increase and to reduce a product defect incidence rate. SOLUTION: A parallel wire length of wires adjacent to each other is extracted by using an layout and a reference value describing a limit value of the parallel wire length as inputs (S1600). Path tracing is executed by using a net list and a clock source point as inputs and clock nets are extracted (S500). The parallel wire length is extracted in the parallel wire length extraction procedure by using gradient information describing a signal waveform gradient at a cell output terminal described in the net list as an input and the clock nets are classified into the side where either of the clock net and its adjacent wire receives the influence of the crosstalk and the side where either of them provides the influence of the cross talk based on the value of the signal waveform gradient at the cell output terminal; and whether the net is located on the side where either of them receives the influence is determined (S501). COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006277753(A) 申请公布日期 2006.10.12
申请号 JP20060107646 申请日期 2006.04.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IWANISHI NOBUFUSA
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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