| 摘要 |
PROBLEM TO BE SOLVED: To test an IP macro having a register of greater data width than that of a data bus by using a test pattern for an IP macro having a register of the same data width as a data bus. SOLUTION: When write accesses to both the top and bottom of a counter in a timer are necessary, a CPU accesses the bottom last; when read accesses to both the top and the bottom are necessary, the CPU accesses the bottom first. The timer stores the data of the data bus in a write buffer during the write accesses to the top, and writes the data of the data bus and the data of the write buffer respectively in the bottom and the top during the write accesses to the bottom. During the read accesses to the bottom, the timer reads bottom data for output to the data bus and reads top data for storage in the read buffer. During the read accesses to the top, the timer outputs the data of the read buffer to the data bus. COPYRIGHT: (C)2007,JPO&INPIT
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