发明名称 LOGIC VERIFICATION DEVICE, LOGIC VERIFICATION METHOD, AND CONTROL PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To provide a logic verification device applicable to logic circuit unit verification and system verification and capable of generating a verification pattern corresponding to pipeline processing for improvement of verification accuracy. <P>SOLUTION: On a plurality of logic verification modules, a transmission device 107, a receipt device 108, and an ID storage device 109 are prepared to be shared between the modules. The logic verification module gives an ID for identifying its own, a read request, and an address to the transmission device, while the transmission device gives the read request and the address to a circuit operation simulation device and stores the ID in the ID storage device at the same time. In receipt of data by the circuit operation simulation device, the receipt device receives the data, reads the ID stored at the first from the ID storage device, and gives the received data to the corresponding logic verification module. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006277630(A) 申请公布日期 2006.10.12
申请号 JP20050099539 申请日期 2005.03.30
申请人 CANON INC 发明人 SAKATA KAZUAKI
分类号 G06F11/22;G01R31/28;G01R31/317 主分类号 G06F11/22
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