| 摘要 |
<P>PROBLEM TO BE SOLVED: To preclude a data of an indefinite value from being taken from an indefinite value generation circuit into a test result compression part therefor, in a scan test using the test result compression part. <P>SOLUTION: The second group of FF circuits F04-F06 is chain-connected all the time in an capture operation of the scan test using the test result compression part MISR, in this semiconductor integrated circuit provided with a combination logic circuit A for processing an input data to be output to the first group of FF circuits F01-F03, and the indefinite value generation circuit BB for outputting a data including the indefinite value to the second group of FF circuits F04-F06. <P>COPYRIGHT: (C)2007,JPO&INPIT |
