| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To attain clock transfer by a small circuit scale. <P>SOLUTION: In the case of inputting data synchronized with 12 MHz clock and generating data synchronized with twice 13.5 MHz clock, data synchronized with 12 MHz clock are latched in a DFF circuit 11 by the inverse clock of 27 MCK which is twice the 13.5 MHz clock, the data synchronized with the 12 MHz clock are latched in a DFF circuit 12 by the inverse clock of 27 MCK and one of outputs from both the DFF circuits 11, 12 is selected by a selector 16. The selector 16 inputs a horizontal synchronizing signal HSYNC synchronized with the 27 MCK clock and the 27 MCK clock, and selects the output of the DFF circuit 12 at timing when the DFF circuit 11 generates mislatching, or selects the output of the DFF circuit 11 at timing when the DFF circuit 12 generates mislatching. A clock outputted from the selector 16 is subjected to re-timing by the 27 MCK clock in a DFF 13. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
