| 摘要 |
PROBLEM TO BE SOLVED: To provide a data transfer controller capable of reducing a processing load of software to improve processing speed. SOLUTION: A DMA transfer request signal generation part 10 asserts a general-purpose I/O side DMAREQ signal to an I/O device 2 when an HDD side DMAREQ signal from an HDD 3 is asserted, a 512-byte counter 11 counts the number of bytes of data outputted by the I/O device 2 until the number becomes the prescribed number of bytes, a protocol conversion part 30 converts the data outputted by the I/O device 2 into data based on a protocol of an ATA interface and outputs them to the HDD 3, and the DMA transfer request signal generation part 10 negates the general-purpose I/O side DMAREQ signal when the number is counted to the prescribed number of the bytes by the 512-byte counter 11, and newly asserts the general-purpose I/O side DMAREQ signal when the HDD side DMAREQ signal is not negated. COPYRIGHT: (C)2007,JPO&INPIT
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