发明名称 |
Memory array including multiple-gate charge trapping non-volatile cells |
摘要 |
An array of multiple-gate memory cells includes sectors. The sectors include at least one row of multiple-gate memory cells. The multiple-gate memory cells comprise a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath each of all or some of the gates in the plurality of gates. Word lines and bit lines source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates. Sector select lines are included to couple selected sectors to the bit lines.
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申请公布号 |
US7120059(B2) |
申请公布日期 |
2006.10.10 |
申请号 |
US20050085325 |
申请日期 |
2005.03.21 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
YEH CHIH CHIEH |
分类号 |
G11C11/34;G11C16/04;H01L27/115 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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