发明名称 |
Manufacturing method of semiconductor device |
摘要 |
In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist such as diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of L<SUB>ov </SUB>area to a desired dimensional range so that the dimension thereof becomes larger. |
申请公布号 |
US7119022(B2) |
申请公布日期 |
2006.10.10 |
申请号 |
US20040852355 |
申请日期 |
2004.05.24 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
UEHARA ICHIRO;SUZAWA HIDEOMI |
分类号 |
G03F7/004;H01L21/302;G03F7/40;H01L21/027;H01L21/28;H01L21/3065;H01L21/336;H01L21/461;H01L21/77;H01L21/84;H01L27/12;H01L29/423;H01L29/786 |
主分类号 |
G03F7/004 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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