| 摘要 |
A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor ( 22 ), within which a second conductor ( 40 ) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer ( 24 ), an interlevel dielectric layer ( 26 ), a trench etch stop layer ( 28 ), an intermetal dielectric layer ( 30 ), and a hardmask layer ( 32 ). The interlevel dielectric layer ( 26 ) and the intermetal dielectric layer ( 30 ) are preferably of the same material. A via is partially etched through the intermetal dielectric layer ( 30 ), and through an optional trench etch stop layer ( 28 ). A trench location is then defined by photoresist ( 38 ), and this trench location is transferred to the hardmask layer ( 32 ). Simultaneous etching of the trench through intermetal dielectric layer ( 30 ), stopping on the trench etch stop layer ( 28 ) if present, simultaneously with the etching of the remainder of the via through the interlevel dielectric layer ( 26 ) that stops on the via etch stop layer ( 24 ), is then performed. After clearing the via etch stop layer ( 24 ) from the via bottom, a copper conductor ( 40 ) is then formed into the trench and via, for example by electroplating and planarization by chemical mechanical polishing over a barrier layer ( 41 ).
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