发明名称 |
Shift register |
摘要 |
An output buffer in each stage of a shift register applies a first clock signal to an output line under control of a first node and a second driving voltage to the output line under control of second and third nodes. A first node controller controls the first node using a start pulse and an output signal of the next stage. A second node controller selectively applies a voltage at a fourth node and the second driving voltage to the second node under control of the first and second clock signals. A third node controller applies the voltage at the fourth node and the second driving voltage to the third node opposite to the second node. A fourth node controller controls the fourth node such that the fourth node has a voltage opposite to the first node using a voltage at the first node and the first driving voltage.
|
申请公布号 |
US7120221(B2) |
申请公布日期 |
2006.10.10 |
申请号 |
US20040988860 |
申请日期 |
2004.11.15 |
申请人 |
LG. PHILIPS LCD CO., LTD. |
发明人 |
MOON SU HWAN |
分类号 |
G09G3/36;G11C19/00;G11C19/28 |
主分类号 |
G09G3/36 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|