<p>A phase-changeable random access memory (PRAM) device according to the invention includes a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column. Additionally, a local word line is driven from both ends at a time, thereby increasing driving capability and reducing access time.</p>
