| 摘要 |
A memory system for use with a master-slave type bus such as an AHB bus (30) has a memory (60), a bus interface (130) to allow memory access from the bus, and a direct memory access interface (130) to allow memory access from a DMA controller without occupying the bus. Compared to the known DMA arrangement, it can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter (130) can arbitrate between the memory accesses and give priority to DMA accesses.
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