发明名称 Seedless wirebond pad plating
摘要 An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. The platable metal layer may be copper and the noble metal plated layer may be of gold, platinum, palladium, rhodium, ruthenium, osmium, iridium or indium.
申请公布号 US7115997(B2) 申请公布日期 2006.10.03
申请号 US20030707075 申请日期 2003.11.19
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 NARAYAN CHANDRASEKHAR;PETRARCA KEVIN SHAWN
分类号 H01L23/48;H01L23/485 主分类号 H01L23/48
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