Managing processor architected state upon an interrupt

摘要

A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow copy of the hard architected permits rapid saving of the hard architected state for the interrupted process, so that the architected state of a next process can be immediately stored in the processor.