| 摘要 |
A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T thereof into N parts, and includes first variable delay sections and second variable delay sections, each of which is formed of an arbitrary number of unit delay buffers connected in series with one another. A phase comparison section makes a compare between the phase of the input clock signal and the phase of an output signal which is the input signal having been delayed while passing through all the first and second variable delay sections, and outputs a result of the comparison. A delay control section calculates a total number of unit delay buffers S required based on the phase comparison result, sets a quotient Q of S divided by N to be the number of unit delay buffers for each of the first variable delay sections, and allocates a remainder R of S divided by N to the second variable delay sections, respectively.
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