发明名称 |
Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction |
摘要 |
In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element. |
申请公布号 |
US7117409(B2) |
申请公布日期 |
2006.10.03 |
申请号 |
US20030735298 |
申请日期 |
2003.12.12 |
申请人 |
NATIONAL TSING HUA UNIVERSITY |
发明人 |
WU CHENG-WEN;HUANG CHIH-TSUN;WANG CHIH-WEA;CHENG KAO-LIANG |
分类号 |
G11C7/22;G11C29/02 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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