发明名称 |
Distributed failure analysis memory for automatic test equipment |
摘要 |
A failure analysis memory is disclosed for use with a semiconductor tester for storing bit image failure information relating to a memory-under-test. The semiconductor tester has a plurality of channel cards disposed proximate the memory-under-test. The failure analysis memory includes a memory controller and a plurality of memory units disposed in communication with the memory controller. The memory units are distributed on the channel cards.
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申请公布号 |
US7117410(B2) |
申请公布日期 |
2006.10.03 |
申请号 |
US20020324707 |
申请日期 |
2002.12.20 |
申请人 |
TERADYNE, INC. |
发明人 |
BORDERS GRADY |
分类号 |
G11C29/04;G01R31/18;G11C15/04;G11C29/56 |
主分类号 |
G11C29/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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