发明名称 |
High speed FIFO synchronous programmable full and empty flag generation |
摘要 |
An apparatus comprising a flag generation circuit configured to generate a full flag signal in response to (i) a read clock signal, (ii) a write clock signal and (iii) a look ahead bitwise comparison configured to detect when a read count signal and a write count signal are equal.
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申请公布号 |
US7116599(B1) |
申请公布日期 |
2006.10.03 |
申请号 |
US20010957587 |
申请日期 |
2001.09.20 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
AU JOHNIE;CHANG CHIA JEN;MEKARA PARINDA |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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