| 摘要 |
A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. To estimate performance, the integrated circuit design is partitioned into strongly coupled components and state points are identified. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.
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