摘要 |
An image signal processing circuit is provided that can narrow the bus width of a bus that outputs data. The circuit is equipped with resistances R<SUB>1</SUB>~R<SUB>511 </SUB>that are serially connected between a first power supply potential V<SUB>T </SUB>and a second power supply potential V<SUB>B</SUB>, comparators C<SUB>1</SUB>~C<SUB>511 </SUB>having first inputs in which potentials V<SUB>1</SUB>~V<SUB>511 </SUB>on terminal sections of the resistances R<SUB>1</SUB>~R<SUB>511 </SUB>are input, respectively, and second inputs in which an analog image signal is input, and an encoder 42 that encodes output signals of the comparators C<SUB>1</SUB>~C<SUB>511 </SUB>into unsigned integer numbers of 9-bit width and outputs the same as digital image data.
|