发明名称 Co-simulation verilog/PLI and system C modules using remote procedure call
摘要 A Verilog/PLI module that simulates behavior of an electronic system is co-simulated in a clock-accurate manner with a System C module that models the behavior of a component of the electronic system using a remote procedure call (RPC). Adding RPC functionality to the Verilog/PLI and System C modules facilitates exchanging parameters between the modules. The RPC is used to transfer process control to the SystemC module, after execution of which control is returned to the Verilog/PLI module. A return value is also returned to the Verilog/PLI module; this return value represents output signals associated with the System C module.
申请公布号 US7117139(B2) 申请公布日期 2006.10.03
申请号 US20010941068 申请日期 2001.08.28
申请人 BIAN QIYONG 发明人 BIAN QIYONG
分类号 G06F9/54;G06F9/46;G06F17/50 主分类号 G06F9/54
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