发明名称 |
FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT |
摘要 |
The present invention discloses a memory wordline decoder that includes a plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation. |
申请公布号 |
KR100629987(B1) |
申请公布日期 |
2006.09.29 |
申请号 |
KR20027002390 |
申请日期 |
2000.07.14 |
申请人 |
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发明人 |
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分类号 |
G11C16/06;G11C16/08;G11C8/10;G11C8/12;H01L21/8247;H01L27/10;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
G11C16/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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