Multi-gate FET e.g. Fin-FET, has channel with multi-layer structure having three elastically stressed layers e.g. silicon stressed layers, where sum of thicknesses of stressed layers is greater than critical thickness of each stressed layer

摘要

The FET has a channel (10) in electric connection with a source and a drain, and gates (20a-20c) to apply an electric field to the channel, when each gate is polarized. The channel has a multi-layer structure with three layers, where one of the layers of the structure has electrical properties different from that of another layer of the structure. The structure has elastically stressed layers (12a-12c) e.g. silicon (Si) stressed layers, where the sum of the thicknesses of the stressed layers in the channel is greater than the critical thickness of each stressed layer. An independent claim is also included for a method for manufacturing a multi-gate FET.