发明名称 Cache eviction technique for reducing cache eviction traffic
摘要 A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.
申请公布号 US2006218352(A1) 申请公布日期 2006.09.28
申请号 US20050087916 申请日期 2005.03.22
申请人 SHANNON CHRISTOPHER J;ROWLAND MARK;SRINIVASA GANAPATI 发明人 SHANNON CHRISTOPHER J.;ROWLAND MARK;SRINIVASA GANAPATI
分类号 G06F12/00;G06F13/28 主分类号 G06F12/00
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