发明名称 |
Integrated circuit margin stress test system |
摘要 |
Systems and methods are disclosed for testing a synchronous memory system by electrically stressing one or more electrical conditions of the component circuits; providing a Built-In Self-Test (BIST) controller to control the electrical stress during device testing; and providing a test stimuli during testing. In another aspect, the memory system testing includes setting a self-timed control input of the memory system to a predetermined self timed period value; and testing the memory based on the predetermined self timed period value.
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申请公布号 |
US2006218455(A1) |
申请公布日期 |
2006.09.28 |
申请号 |
US20050089300 |
申请日期 |
2005.03.23 |
申请人 |
SILICON DESIGN SOLUTION, INC. |
发明人 |
LECLAIR KEVIN R.;WIK THOMAS R.;LE CHUONG T.;NGUYEN HIEU D.;TRAN DUYTAN K.;BLIGH KEVIN O. |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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