| 摘要 |
PROBLEM TO BE SOLVED: To reduce a processing load in a master processor such as a DSP and a CPU, in a signal processor. SOLUTION: In this signal processor 100 of the present invention, the master processor such as the DSP 10 executes actively various processings in the processor, and a slave processor such as a coprocessor executes specified unit processing in response to an execution start indication. A schedule control circuit 50 issues the execution start indication instead of the master processor. The schedule control circuit 50 detects an arrival of a start time in the every unit processing, and outputs the execution start indication to the slave processor to execute the unit processing. COPYRIGHT: (C)2006,JPO&NCIPI
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