| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a load of a processor when executing a plurality of computation operations. <P>SOLUTION: This signal processor 10 includes an input memory 12, a selection part 14, a computing part 16, an output memory 18 and a microscheduler 20. The processor 22 transfers a data between the input memory 12 and the output memory 18 via a processor bus 26. The processor 22 is connected to the microscheduler 20. The data may be transferred between the processor 22 and the microscheduler 20, via the processor bus 26. The output memory 18 is connected to the selection part 14 by a exclusive bus 24. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
