| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus in which a good cache bit rate can be achieved without being restricted by refresh operation when a sense amplifier column is used as a cache memory. SOLUTION: In the semiconductor memory apparatus, a mat 10 being an unit block of a memory cell array in which a plurality of memory cells MC are formed at intersecting points of a plurality of word lines WL and a plurality of bit lines BL is provided with, two sense amplifier columns 11 consisting of a plurality of sense amplifiers SA, and a switch control part 12 which can switch a connection state between respective sense amplifier columns 11 at both end parts of a plurality of bit lines BL. The sense amplifier columns 11 of one side set as a cache memory at the time of performing refresh operation of the mat 10 in a data holding state of the cache memory, are separated from the plurality of bit lines BL and refresh operation is performed by using only the sense amplifier column 11 of the other side being not in a data holding state as the cache memory. COPYRIGHT: (C)2006,JPO&NCIPI
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