| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem wherein it is difficult to execute bus adjustment while reflecting the importance of individual data transfer. SOLUTION: A bus adjustment circuit 47 adjusts bus use requests issued from a plurality of bus masters. An address decode circuit 61 receives an access address signal issued from a bus master and outputs a data block the access of which is requested. A data transfer access priority setting table circuit 49 holds priority of each data block, and outputs the priority of the data block the access of which is requested on the basis of the output from the address decode circuit 16. A priority determination circuit 48 determines a bus master which requests the access to a data block having the highest priority on the basis of the output from the data transfer access priority setting table circuit 49, and permits the use of the bus to this bus master. COPYRIGHT: (C)2006,JPO&NCIPI
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