| 摘要 |
This clock generator comprises an oscillator for generating an alternating current pilot signal and a pulse formatting circuit which is intended to convert the pilot signal from the oscillator into a pulse clock signal having a duty factor of at least approximately 50%. According to one implementation, a series of at least two inverters is provided, the input of the first inverter being controlled by the alternating current pilot signal and the output of the second inverter supplying the clock signal. A power supply means may also be provided to supply the inverters with a regulated power supply voltage dependent on the signals appearing at the outputs of the inverters.
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