发明名称 |
Digital data decompression implemented in a field programmable array device |
摘要 |
Operations for decompression of compressed data is performed in parallel and in a pipelined manner to generate addresses into a memory on-the-fly rather than using a large look-up table. The logic circuits for doing so are thus reduced to the point of being able to be formed by suitable programming of a field programmable gate array (FPGA) while achieving substantial increase in processing speed beyond speed increases attributable to increase of clock rates.
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申请公布号 |
US2006214822(A1) |
申请公布日期 |
2006.09.28 |
申请号 |
US20060387052 |
申请日期 |
2006.03.23 |
申请人 |
MITCHELL JOAN L;HOSKINS PHILLIP K |
发明人 |
MITCHELL JOAN L.;HOSKINS PHILLIP K. |
分类号 |
H03M7/00 |
主分类号 |
H03M7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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